Intellectual Property India Publishes Patent Application for 'Fpga Based Efficient Error Reduction Address Generator For Wimax Deinterleaver' Filed by Bharath Institute Of Higher Education And Research

MUMBAI, India, April 25 -- Intellectual Property India has published a patent application (202341070303 A) filed by Bharath Institute Of Higher Education And Research, Chennai, Tamil Nadu, on Oct. 17, 2023, for 'fpga based efficient error reduction address generator for wimax deinterleaver.'

Inventor(s) include N. Smaran; Mr. S. Siva Kumar; Dr. S Arulselvi; Dr. H. Umma Habiba; B. Hemalatha; S. Balaji; and Dr. B. Karthik.

The application for the patent was published on April 25, under issue no. 17/2025.

According to the abstract released by the Intellectual Property India: "Low-multifaceted nature and novel system is proposed to proficiently execute the location age hardware of the 2-D deinterleaver utilized in the WiMAX trans collector u...