Intellectual Property India Publishes Patent Application for 'Dynamic Routing And Traffic Optimization Mechanisms For Network-On-Chip Architectures' Filed by Parthasarathi P; K. Sathiskumar; T. Janani; and P. Sathishkumar

MUMBAI, India, Oct. 31 -- Intellectual Property India has published a patent application (202441033557 A) filed by Parthasarathi P; K. Sathiskumar; T. Janani; and P. Sathishkumar, Namakkal, Tamil Nadu, on April 27, 2024, for 'dynamic routing and traffic optimization mechanisms for network-on-chip architectures.'

Inventor(s) include Parthasarathi P; K. Sathiskumar; T. Janani; and P. Sathishkumar.

The application for the patent was published on Oct. 31, under issue no. 44/2025.

According to the abstract released by the Intellectual Property India: "Network-on-chip (NoC) architectures have emerged as a promising solution for on-chip communication in modern multi-core and many-core systems. NoCs provide scalable and efficient communication i...