Intellectual Property India Publishes Patent Application for 'Binary Adders Of Low Transistor Count' Filed by Neologic Ltd.

MUMBAI, India, March 7 -- Intellectual Property India has published a patent application (202417072859 A) filed by Neologic Ltd., Tel Mond, Israel, on Sept. 26, 2024, for 'binary adders of low transistor count.'

Inventor(s) include Messica, Avi; and Leshem, Ziv.

The application for the patent was published on March 7, under issue no. 10/2025.

According to the abstract released by the Intellectual Property India: "A method for implementing a logic circuit employing a combination of binary adders of different lengths having summation and carry outputs and AND gates, comprising the steps of replacing at least one known CMOS implemented binary adder with an improved binary adder consisting of a logic block for performing summation between bi...