MUMBAI, India, Jan. 2 -- Intellectual Property India has published a patent application (202541122801 A) filed by Vellore Institute Of Technology, Vellore, Tamil Nadu, on Dec. 5, 2025, for 'approximate unsigned multiplier with compressor-based partial product reduction.'

Inventor(s) include Dr. Aarthy M; and Ms. Kowshalya R.

The application for the patent was published on Jan. 2, under issue no. 01/2026.

According to the abstract released by the Intellectual Property India: "The present disclosure provides an approximate unsigned multiplier system (300) that includes an input processing unit (302) configured to receive a first binary operand and a second binary operand, a partial product generation stage (308) coupled to the input proces...