INTERNATIONAL PATENT: JIANGSU SILICON INTEGRITY SEMICONDUCTOR TECHNOLOGY CO., LTD, 江苏芯德半导体科技有限公司 FILES APPLICATION FOR "WAFER-LEVEL ULTRATHIN QUAD FLAT NO-LEAD CHIP PACKAGING METHOD AND CHIP PACKAGING STRUCTURE"

GENEVA, May 25 -- JIANGSU SILICON INTEGRITY SEMICONDUCTOR TECHNOLOGY CO., LTD (8 Lin Chun Rd., Pukou Electronic Design Automation, PukouNanjing, Jiangsu 210000), 江苏芯德半导体科技有限公司 (中国江苏省南京市浦口区浦口经济开发区林春路8号) filed a patent application (PCT/CN2024/091315) for "WAFER-LEVEL ULTRATHIN QUAD FLAT NO-LEAD CHIP PACKAGING METHOD AND CHIP PACKAGING STRUCTURE" on May 07, 2024. With publication no. WO/2025/102621, the details related to the patent application was published on May 22, 2025.

Notably, the patent applica...